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PME in PCIE

  • Sivabalan Shanmugavel
  • Feburary 10, 2026

PCIe PME_Turn_Off

Background:

PCI Express (PCIe) devices support multiple power states—from fully active (D0) to various sleep states (D1/D2/D3hot/D3cold)—allowing systems to save energy without sacrificing responsiveness. One key mechanism that enables safe transitions, particularly from D3hot to D3cold, is the PME_Turn_Off message.

PME_Turn_Off was introduced to allow the root complex or switches to broadcast a “turn off” signal downstream, instructing all devices to stop generating power management events and to prepare for link disablement and power removal. This message coordinates device and link transitions into low-power states like L2/L3 Ready and ensures orderly shutdown of the physical and logical layers.

Introduction:

In the PCIe architecture, PME stands for Power Management Event. Traditionally, PME referred to a signal or message generated by a PCI or PCIe device to wake the system from a low-power state. However, PCIe extends this concept into a more robust messaging protocol that includes two key TLP message types used for controlled power-down:

  1. PME_Turn_Off — sent from the Root Complex (RC) to a device or downstream hierarchy, instructing it to prepare for power removal.
  2. PME_TO_Ack (PME Turn Off Acknowledge) — sent from the device back to the RC, confirming that it is safe to power off.

Together, these two TLP messages form the PME Turn Off handshake, which ensures that all in-flight PCIe transactions have completed, and that the device is ready for power to be removed.

How PCIe PME works? (the sequence)

he PCIe power management model defines four device power states (D0 through D3cold) and multiple link power states (L0, L0s, L1.x, L2).

The PME_Turn_Off message is specifically involved in transitions from D3hot → D3cold — when the main power to the device will be turned off.

Here’s the typical sequence:

  1. The operating system (via ACPI or driver) instructs the Root Complex to power down a device.
  2. The RC transitions the device to D3hot using the Power Management Control/Status register (PMCSR).
  3. The RC then sends a PME_Turn_Off message (Code 0x18) to the device or hierarchy.
  4. The device flushes outstanding DMA, finishes pending completions, and quiesces the link.
  5. Once it’s safe, the device sends back PME_TO_Ack message (Code 0x19).
  6. The RC finally disables slot power or removes the main power rail (D3cold).

This ensures that no packets are lost and that the link is quiet before power is removed.

PME_Turn_Off Support:

According to the PCI Express Base Specification, this feature is mandatory only for devices that can enter D3cold or support hot-plug power removal.

Required:

  1. Root Complex ports
  2. Switch upstream/downstream ports
  3. Devices that support D3cold
  4. Devices in hot-pluggable slots

Optional:

  1. Endpoints that remain powered (never enter D3cold)
  2. Fixed embedded devices where power removal is not controlled by PCIe logic

If a device doesn’t support PME_Turn_Off, the operating system or driver must ensure data integrity by other means — typically through software-controlled quiesce and link power management.

Conclusion:

The PME_Turn_Off event helps coordinate power-down sequences by signalling the SSD to stop normal operations and transition into low-power states like L2/L3 or D3 cold state. This reduces power consumption and heat generation dramatically when the SSD is idle or not in use, which can notably lower SSD temperatures and prevent overheating. Reduced temperatures help in maintaining drive reliability and preventing thermal throttling, which preserves SSD performance.

PME_Turn_Off is vital for managing PCIe SSD power states properly to achieve energy efficiency, reduce heat, and maintain reliable operation in real-world use cases